Specific on-resistance and blocking voltage of a semiconductor power device are defined by a bandgap of a semiconductor substrate (hereinafter, simply called “substrate”) material, and they are in a trade-off relationship. Thus, to top the performance of silicon devices which have been widely used as power devices, it is effective to use substrate materials having a larger bandgap than silicon. Particularly, SiC (silicon carbide) has some advantages such as having a sufficiently-large bandgap about three times the bandgap of silicon, being easy to form p-type and n-type conductivities, and being capable of forming an oxide film by a thermal treatment. Therefore, SiC has been receiving much attention as it has potential for a high-performance MOSFET (metal oxide semiconductor field effect transistor).
However, there is a big problem in forming an oxide film on silicon carbide. That is, carbon remains in the oxide layer when silicon carbide is subjected to a heat treatment, resulting in formation of high-density interface states. Thereby, the channel mobility of the MOSFET is greatly degraded, and accordingly, the specific on-resistance is significantly increased. Also, carbon in the oxide film causes degradation of the oxide film reliability, which is a major barrier to forming the MOSFET.
Structures of a device avoiding the problem of the oxide film interface include the junction FET. The junction FET is a device of a type of taking a pn junction as its gate and controlling a channel, what is called “normally-on” type that is turned off by applying, normally, a negative voltage to the gate to extend the depletion layer in the channel. Since the normally-on type devices has limited usage in view of fail safe in case of having the gate failed in the ON state, the power devices are desired to be the normally-off type, generally. A junction FET of silicon cannot have a high blocking voltage when it is the normally-off type, but when silicon carbide is used, a high blocking voltage can be achieved by narrowing the channel width even if it is the normally-off type. That is because the built-in potential of a pn junction of silicon carbide is as high as about 2.5 V and the channel can be completely depleted without applying a negative voltage to the gate. Therefore, a high-performance device which is the normally-off type and does not depend on the oxide film interface can be achieved. Note that, Japanese Patent Application Laid-Open Publication No. 2004-134547 (Patent Document 1) discloses an example of a normally-off type silicon carbide junction FET. Meanwhile, generally, to achieve the normally-off type by a junction FET, it is necessary to set the channel length to be larger than or equal to about 1 μm and the channel width to be smaller than or equal to about 0.5 μm, and therefore, there is a problem still remained that the specific on-resistance becomes large as the resistance of the channel becomes large.
On the other hand, as means for reducing the channel resistance of the junction FET, an increase of concentration of the channel layer is cited. By increasing the impurity concentration of the channel to be higher than the impurity concentration of the drift layer, carriers in the channel are increased so that the channel resistance is reduced. Japanese Patent Application Laid-Open Publication (Translation of PCT Application) No. 2001-527296 (Patent Document 2) discloses a junction FET having an increased impurity concentration in the channel layer.